1. Field of the Invention
The present invention generally relates to a semiconductor integrated circuit and a testing method thereof, and especially relates to the semiconductor integrated circuit, operational margins of which can be tested by causing a voltage applied to a step-up power supply line to fluctuate, and the testing method thereof.
2. Description of the Related Art
Battery-driven electronic apparatuses, such as a notebook type PC (Personal Computer) and a cellular telephone terminal, are expanding use of DRAM (Dynamic Random Access Memory). In order to prolong life of a battery used by the apparatuses, the apparatuses are required to operate with minimum power consumption.
Then, in order to reduce the power consumption in DRAM, conventional practices have been to lower the external power supply voltage, and to use the lowered voltage as the operational power supply voltage.
A conventional semiconductor integrated circuit is explained with reference to a semiconductor integrated circuit DRAM 5 shown in FIG. 1. The semiconductor integrated circuit DRAM 5 shown in FIG. 1 consists of a memory core 1, an interface circuit 2, a logic circuit 3, and a power supply circuit 4. The interface circuit 2 receives an address signal and a control signal from an address control line Add-Contl, and a data signal through a data line (DQ) from a CPU (Central Processing Unit) that is not illustrated, provides the above-mentioned signals to the logic circuit 3, receives signals from the logic circuit 3, and provides the received signals to the CPU through the data line (DQ). The logic circuit 3 generates a control signal that determines operation timing of each of the internal circuits, based on the address signal, the control signal, and the like received from the CPU, performs writing to and reading from the memory core 1, and generates writing data and reading data. The power supply circuit 4 supplies predetermined voltages to the memory core 1, the interface circuit 2, and the logic circuit 3, receiving power from an external power supply (a high voltage Vdd and a ground voltage Vss).
Power supplies that the power supply circuit 4 provides are explained with reference to FIG. 2. The power supply circuit 4 provides a step-down power supply 12, a step-up power supply 13, a pre-charge power supply 14, and a negative power supply 15 to an internal circuit 6 that includes the memory core 1, the interface circuit 2, and the logic circuit 3.
The step-down power supply 12, the step-up power supply 13, the pre-charge power supply 14 and the negative voltage power supply 15 generate and provide respectively predetermined voltages, referring to a reference voltage that a reference voltage generator 11 outputs.
The step-down power supply 12 generates a voltage that serves an internal power supply voltage, which is supplied to, e.g., a bit line of the memory core 1, the interface circuit 2, and the logic circuit 3. The step-up power supply 13 generates an elevated voltage, which is supplied to, e.g., a word line of the memory core 1. The pre-charge power supply 14 supplies a pre-charge voltage, e.g., to the memory core 1. The negative voltage power supply 15 provides a back bias to a transistor that constitutes a memory cell of the memory core 1, the memory cell storing an electric charge.
FIG. 3 shows relationships among voltages output from the step-down power supply 12, the step-up power supply 13, the pre-charge power supply 14, and the negative power supply 15, when the external power supply is turned on, and as the external power supply voltage Vcc increases from zero volts. The voltage output from the negative power supply 15 serves as Vbb 21 (a negative voltage), when the external power supply voltage Vcc reaches a predetermined voltage. The voltage output from the pre-charge power supply 14 serves as Vpr 22 (a pre-charge voltage), when the external power supply voltage Vcc reaches a predetermined voltage. Similarly, the voltages output from the step-down power supply 12 and the step-up power supply 13 are set to Vii 23 (an internal power supply voltage) and Vpp 24 (an elevated voltage), respectively, when the external power supply voltage Vcc reaches a predetermined voltage.
FIG. 4 shows an example of a reference voltage generating circuit of the reference voltage generator 11. The reference voltage generating circuit includes pMOS 31, pMOS 32, nMOS 33, nMOS 34, a buffer amplifier 35, and a resistance element 36.
The pMOS 31 and pMOS 32 serve as a current mirror circuit. Here, if the power supply voltage Vcc rises, then, current through the pMOS 31 increases, and the nMOS 34 enters a deep conductive state, which increases the voltage drop through the resistance element 36, and the voltage of a point B rises. Consequently, the nMOS 33 enters a deep conductive state, and the voltage of a point A falls. Conversely, if the power supply voltage Vcc falls, the voltage of the point A rises. Thus, the point A provides a voltage that is stable against a change of the power supply voltage Vcc.
Although the voltage of the point A is compensated against changes of temperature and the external power supply voltage, an influence of a variation in the transistor that constitutes the circuit remains. In order to cope with this, the buffer amplifier 35 is connected to the point A such that the variation in the transistor is removed, and the reference voltage generator 11 outputs the reference voltage (Vref).
FIG. 5 shows an example of a pMOS regulated power supply, which is explained hereunder. The pMOS regulated power supply shown at (A) of FIG. 5 includes pMOS 41, pMOS 42, pMOS 43, nMOS 44, nMOS 45, and nMOS 46. Here, the pMOS 41 and pMOS 42 serve as a current mirror circuit; the nMOS 44, nMOS 45, and nMOS 46 serve as a differential amplifier 48; and the pMOS 43 functions as a driver 47. The pMOS regulated power supply receives the external power supply voltage Vcc, which serves as the elevated voltage, and the grounding voltage Vss as the lowest voltage. The pMOS regulated power supply shown at (A) of FIG. 5 can be represented in a simple way as shown in (B) of FIG. 5.
Next, operations of the pMOS regulated power supply are described. The differential amplifier 48 compares the output voltage Vii of the driver 47 with the reference voltage Vref, and controls such that the difference between the two voltages, namely, Vref-Vii, becomes zero. Consequently, the output voltage Vii of the driver 47 finally becomes the same voltage as the reference voltage Vref.
The pMOS regulated power supply shown in FIG. 5 has features such as follows:
(1) the output voltage Vii obtained is independent of load current because of a negative feedback to the output voltage Vii of the driver 47;
(2) since the external power supply voltage is applied to the source electrode of the driver 47, sensitivity tends to be high to the noise of the external power supply voltage Vcc; and
(3) in order to enhance the stability of the output voltage Vii against load current change, it is necessary to improve the response of the differential amplifier 48, which causes the current drain of the differential amplifier 48 to become large in the magnitude of mA.
Advantages of the pMOS regulated power supply include a high flat property of the generated voltage, and a space-saving feature. Disadvantages include high susceptibility to noise, and large power consumption required. Here, the high flat property refers to a property that there is little fluctuation in the output voltage when the load varies and/or little influence when the external power supply voltage is made close to the internal power supply voltage.
FIG. 6 shows an example of an nMOS regulated power supply, which is explained in the following. The nMOS regulated power supply shown at (A) of FIG. 6 includes a first driver 57 that consists of pMOS 53, a second driver 61 that consists of nMOS 59, a Vth canceller 62 that consists of nMOS 60 serving as a diode, and a resistance element 63. Here, the pMOS 51 and pMOS 52 constitute a current mirror circuit, and the nMOS 54, nMOS 55, and nMOS 56 constitute a differential amplifier 58.
The pMOS regulated power supply receives the step-up voltage Vpp, serving as the highest voltage, from the step-up power supply 13, the external power supply voltage Vcc, and the grounding voltage Vss, serving as the lowest voltage. The pMOS regulated power supply can be expressed as shown at (B) of FIG. 6.
The differential amplifier 58 of the nMOS regulated power supply shown in FIG. 6 receives the reference voltage Vref and a negative feedback voltage Vin. Because of the presence of the Vth canceller 62, a voltage equal to (Vin+Vth) is applied to the gate of the nMOS 59 of the second driver 61 (this means that the output voltage is lower than to the gate voltage of nMOS 55 by an amount equal to Vth by the Vth canceller 62). In this manner, a voltage that is lower than the gate voltage of the nMOS 59 by Vth is output from the source of the nMOS 59, that is, Vin is obtained.
Operations are explained in the following. The output voltage (Vin+Vth) of the first driver 57 is converted to Vin by the Vth canceller 62, and the Vin is supplied to the differential amplifier 58. The differential amplifier 58, the first driver 57, and the Vth canceller 62 control such that the output Vin output by the Vth canceller 62 and the reference voltage Vref become the same voltage. Consequently, the output voltage (Vin+Vth) of the driver 57 becomes equal to (Vref+Vth), and a voltage equal to the reference voltage Vref, which is lower than the gate voltage of nMOS 59 by Vth, is obtained from the source of the nMOS 59.
If there is no Vth canceller 62 present, a voltage equal to (Vref-Vth) is output from the second driver 61. Since the output voltage Vii becomes dependent of Vth, the output voltage Vii depends on temperature.
The nMOS regulated power supply shown in FIG. 6 has features as follows:
(1) since no feedback is applied to the output voltage Vii of the driver 61, the output voltage depends on the magnitude of load current, and further, when the power supply voltage Vcc of the driver 61 approaches the output voltage Vii according to a state of operation, a voltage (Vds) between the drain and the source of the nMOS 59 becomes small, causing a problem that the flat property is degraded;
(2) the driver 61 is constituted by nMOS (s), obtaining a high stability against noise in the external power supply voltage Vcc; and
(3) output of the driver 57 is stable, requiring a slower response of the differential amplifier 58, which suppresses current drain of the differential amplifier 58 to the magnitude of xcexcA.
While the nMOS regulated power supply has a high noise-resistant property, the flat property of the output voltage is low.
As described above, each of the pMOS regulated power supply and the nMOS regulated power supply has respective advantage and disadvantage.
In view of the low power consumption, the nMOS regulated power supply is often used.
In the nMOS regulated power supply shown in FIG. 6, the step-up voltage (Vpp) is used for the circuit that generates the gate voltage (VG) of the nMOS 59 in consideration of the influence of the loss of Vth of the second driver 61 that consists of nMOS 59.
Operation margin of a semiconductor integrated circuit is checked often by applying the Vpp from an external source, and by changing the voltage of Vpp. If Vpp is arbitrarily changed at the checking, the gate voltage of nMOS 59 of the second driver 61 is also changed. In order to avoid this situation, two Vpp generating circuits have been conventionally used, one being a Vpp generating circuit 73 for the memory core, and the other a Vpp generating circuit 71 for step-down power supply (for example, the nMOS regulated power supply as shown in FIG. 6) that generates Vii, as shown in FIG. 7.
Each of the Vpp generating circuit 73 for the memory core and the Vpp generating circuit 71 for step-down power supply consists of a Vpp detection circuit 81, an oscillation circuit 82 for Vpp generating, and a step-up circuit 83, as shown at (A) in FIG. 8. The Vpp detection circuit 81 detects the output voltage of the step-up circuit 83, and controls oscillation operation of the oscillation circuit 82 for Vpp generating, and the step-up circuit 83 operates by the output of the oscillation circuit 82 for Vpp generating.
An example of the Vpp detection circuit is explained with reference to FIG. 8. The Vpp detection circuit shown at (B) FIG. 8 consists of a resistance element 91, having a resistance value R91, a resistance element 92, having a resistance value R92, pMOS 93, nMOS 94, nMOS 95, pMOS 96 and nMOS 97, an inverter 98, and an inverter 99.
The pMOS 93 and pMOS 96 constitute a current mirror circuit, and nMOS 94, nMOS 95, and nMOS 97 constitute a differential amplifier.
The voltage of Vpp is divided by the resistance element 91 and the resistance element 92, and a voltage Vppxe2x80x2 is obtained, the value of which is obtained from a formula (1) that follows.
Vppxe2x80x2=Vppxc3x97R92/(R91+R92)xe2x80x83xe2x80x83(1) 
The voltage Vppxe2x80x2 is applied to the gate of the nMOS 94.
Further, the reference voltage Vref is applied to the nMOS 95 and nMOS 97.
When Vppxe2x80x2 reaches Vref or becomes larger than Vref, namely,
Vppxe2x80x2 greater than =Vrefxe2x80x83xe2x80x83(2) 
a high level signal H is output from the drain electrode of nMOS 97. The H signal is provided to the inverter 98, and then, to the inverter 99 that outputs the H signal as a Vdet signal.
On the other hand, when Vppxe2x80x2 is less than Vref, namely,
Vppxe2x80x2 less than Vrefxe2x80x83xe2x80x83(3) 
a low level signal L is output from the source electrode of the nMOS 97. The L signal is provided to the inverter 98, and then, to the inverter 99 that outputs the L signal the Vdet signal.
In the case as shown in FIG. 7, the Vpp detection circuit has to be provided to both the Vpp generating circuit 73 for the memory core, and the Vpp generating circuit 71 for the step-down power supply, which causes a problem from a view point of the power consumption.
Further, conventionally, in order to avoid the problem of power consumption, when testing, the Vii 23 (internal power supply voltage) is bridged to the step-up power supply line (Vpp power supply line), and the external power supply voltage that fluctuates is supplied to the step-up power supply line.
However, in the case of, e.g., Vii=1.5V and Vcc maximum=3.3V, more than twice the internal voltage is applied to the internal circuit, increasing charging/discharging current of a signal, resulting in a problem of a higher noise level of the power supply, and blocking of a circuit operation timing margin.
Furthermore, when a problem arises in a circuit when testing, it is impossible to determine whether the problem is due to the Vii becoming too high, or the voltage (Vgs) between gate and source becoming too high.
The present invention is made in view of the above-mentioned problems, and the objective of the present invention is to provide a testing method of a semiconductor integrated circuit, operational margins of which can be tested at low power consumption, and a semiconductor integrated circuit, operational margins of which can be tested at lower power consumption.
It is a general object of the present invention to provide a semiconductor integrated circuit, operation margins of which can be tested by applying a fluctuating voltage to a step-up power supply line, and a testing method therefor that substantially obviate one or more of the problems caused by the limitations and disadvantages of the related art.
Features and advantages of the present invention will be set forth in the description that follows, and in part will become apparent from the description and the accompanying drawings, or may be learned by practice of the invention according to the teachings provided in the description.
Objects as well as other features and advantages of the present invention will be realized and attained by the semiconductor integrated circuit, operational margins of which can be tested by applying fluctuating voltages to the step-up power line, and the testing method therefor particularly pointed out in the specification in such full, clear, concise, and exact terms as to enable a person having ordinary skill in the art to practice the invention.
To achieve these and other advantages and in accordance with the object of the present invention, as embodied and broadly described herein, the semiconductor integrated circuit of the present invention includes a first step-up power supply unit, and a second step-up power supply unit, among other things.
In the semiconductor integrated circuit of the present invention, an internal power supply circuit generates internal power based on power supplied from the first step-up power supply unit during normal operations.
The internal power supply circuit generates the internal power based on power supplied from the second step-up power supply unit during a test, with the first step-up power supply being put into stand-by mode.
In order to switch between the first step-up power supply and the second step-up power supply, switches are provided. The switches are capable of being operated by a test signal that is supplied from an external source. In this manner, power consumption required when testing the operational margins is lowered.
The semiconductor integrated circuit of the present invention can also be configured with one step-up power supply that provides power to the internal power supply circuit.
The semiconductor integrated circuit is tested by the testing method of the present invention, in which an external source provides power to the step-up power supply line, and another step-up power supply generates the internal power during testing.
During normal operations, the step-up power supply provides power to the step-up power supply line, and the step-up power supply generates the internal power.
The testing method includes switching of the power supply circuits for normal operations and for testing by operating switches in accordance with a test signal supplied from an external source.
The testing method of the present invention is suitable for testing the semiconductor integrated circuits of the present invention, which can be tested by fluctuating a voltage applied to the step-up power supply line.